The most widely established technology for interconnecting power semiconductor chips and connecting them to conductor tracks is thick-wire bonding. Ultrasound energy is used to create a permanent connection between the Al wire, which has a typical diameter of several hundreds of μm, and the contact surface, which is of Al on the chip and Cu on the power module, via an intermetallic connection.
There are alternative techniques to bonding such as ThinPak. In this technique, contact is made with the chip surface via solder applied over holes in a ceramic plate.
In MPIPPS (Metal Posts Interconnected Parallel Plate Structures) the contacts are made by soldered copper posts.
Another way of making contact is via solder bumps for flip-chip technology. This method additionally enables improved heat dissipation because the power semiconductors can be soldered onto DCB substrates on the upper and lower face (DCB stands for Direct Copper Bonding).
Contact is also made over a wide area via vapor-deposited Cu leads, the insulation of the conductor tracks being achieved by vapor-phase deposition of an insulator (CVD process) (Power Module Overlay Structure).
Finally, making contact using a patterned foil via an adhesive or solder process is also known.
U.S. Pat. No. 5,616,886 proposes the bondless module without specifying any process details.
Ozmat B., Korman C. S. and Filion R.: “An Advanced Approach to Power Module Packaging”, 0-7803-6437-6/00, IEEE 2000 discloses a method in which power semiconductors are positioned on a tensioned film within a frame.
A method is known from Ostmann A., Neumann A.: “Chip in Polymer—the Next Step in Miniaturization”, in “Advanced Microelectronics”, Volume 29, No. 3, May/June 2002, in which logic chips located on a substrate are embedded in a polymer.